A low-noise phase-locked loop design by loop bandwidth optimization

Author

Lim, Kyoohyun ; Park, Chan-Hong ; Kim, Dal-Soo ; Kim, Beomsup

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

35

Issue

6

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

807

Lastpage

815

Abstract

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

Keywords

CMOS analogue integrated circuits; circuit optimisation; integrated circuit modelling; phase locked loops; timing jitter; 0.6 micron; 22 ps; 3.1 ps; CMOS technology; discrete-time PLL model; loop bandwidth optimization; low-noise phase-locked loop design; optimal bandwidth; overall PLL jitter; peak-to-peak jitter; timing jitter; Bandwidth; CMOS technology; Circuit testing; Circuit topology; Design methodology; Design optimization; Phase locked loops; Prototypes; Semiconductor device modeling; Timing jitter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.845184

Filename

845184