• DocumentCode
    1343222
  • Title

    A Fault Tolerant Memory For Duplex Systems

  • Author

    Hartwell, W.T. ; Hoffner, C.W. ; Toy, W.N.

  • Author_Institution
    Bell Telephone Laboratories; Naperville Road; Naperville, Illinois 60540 USA.
  • Issue
    2
  • fYear
    1978
  • fDate
    6/1/1978 12:00:00 AM
  • Firstpage
    134
  • Lastpage
    138
  • Abstract
    A fault-tolerant memory design uses modular bit swapping to achieve high system availability with minimum redundancy despite high memory-device failure rates. The design permits automatic repair of multiple faults without loss of error detection, thereby allowing deferral of manual repair. Although the design was directed toward use in a duplex system, the technique potentially applies to simplex systems. Double-bit swapping and 4096-word modules were chosen for this system. With a 64k memory, 18 memory device faults would occur in its 40-year life. The number of instances of manual repair will average 3; the number of faults in the system when manual repair is required will average 6. Similarly, with a 1024k memory, 288 memory faults would occur in its 40-year life. The number of instances of manual repair will average 20 and the number of faults in the system when manual repair is required will average 14.
  • Keywords
    Availability; Computer errors; Costs; Error correction; Fault detection; Fault tolerance; Fault tolerant systems; Maintenance; Random access memory; Read-write memory; Fault tolerant memory design; Memory error correction; Memory reliability;
  • fLanguage
    English
  • Journal_Title
    Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9529
  • Type

    jour

  • DOI
    10.1109/TR.1978.5220284
  • Filename
    5220284