DocumentCode
1343633
Title
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time 
ADC With VCO-Based Integrator and Quantizer Implemented in 0.13  ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm<sup>2</sup> demonstrated. A key innovation is the explicit use of the oscillator´s output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>CMOS digital integrated circuits; analogue-digital conversion; delta-sigma modulation; voltage-controlled oscillators; CMOS; VCO-based integrator; VCO-based quantizer; bandwidth 20 MHz; continuous-timeΔΣ analog-to-digit al converter; fourth-order noise shaping; opamp-based integrators; power 87 mW; size 0.13 μm; voltage 1.5 V; Analog-digital conversion; Bandwidth; Filtering; Filters; Frequency; Prototypes; Sampling methods; Transceivers; Voltage-controlled oscillators; Wideband; <formula formulatype=)
$DeltaSigma$ ; Analog-to-digital conversion; VCO-based; quantizer; ring-oscillator; voltage-controlled oscillator (VCO);
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2032703
Filename
5342354
Link To Document