DocumentCode
1343641
Title
A 150 GHz Amplifier With 8 dB Gain and 
6 dBm 
in Digital 65 nm CMOS Using Dummy-
Author
Seo, Munkyo ; Jagannathan, Basanth ; Pekarik, John ; Rodwell, Mark J.W.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of California at Santa Barbara, Santa Barbara, CA, USA
Volume
44
Issue
12
fYear
2009
Firstpage
3410
Lastpage
3421
Abstract
A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yields 5.7 dB of MSG at 150 GHz. Measurement shows the amplifier exhibits 8.2 dB of gain, 6.3 dBm of Psat, 1.5 dBm of PidB and 27 GHz of 3 dB bandwidth, while consuming 25.5 mW at 1.1 V. The dummy-prefilled microstrip line exhibits QTL ¿ 12 up to 200 GHz.
Keywords
CMOS digital integrated circuits; amplifiers; circuit layout; microstrip lines; network topology; amplifier; density-rule compliant matching element; digital CMOS process; dummy modeling; dummy-prefilled microstrip lines; frequency 150 GHz; frequency 27 GHz; gain 8.2 dB; power 25.5 mW; size 65 nm; voltage 1.1 V; Bandwidth; CMOS process; CMOS technology; FETs; Fingers; Gain; Microstrip; Millimeter wave integrated circuits; Semiconductor device modeling; Silicon; 150 GHz amplifier; 65 nm; CMOS millimeter-wave integrated circuits; MMICs; amplifiers; dummy modeling; matching loss; metal filling; millimeter-wave integrated circuits; pattern density rules; silicon; transmission lines;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2032273
Filename
5342355
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