Oversampling current sample/hold structures for digital CMOS process implementation

Author

Mehr, Iuri ; Sculley, Terry L.

Author_Institution

Analog Devices Inc., Wilmington, MA, USA

Volume

45

Issue

2

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

196

Lastpage

203

Abstract

The inaccuracies obtained by sampling a dynamic input signal is a major source of error in current-mode circuits. A sampled-data feedback architecture is presented for the design of a high-linearity current sample/hold that uses oversampling to overcome the nonlinearity of internal components. Both system and circuit level considerations are discussed, culminating in the design and implementation of both first- and second-order structures in a 2 μm p-well CMOS process. Limited test results show a linearity of up to 69 dB at a sampling rate of 5 MHz. These circuits provide an excellent sampling stage for the realization of a high-resolution current-mode ΔΣ A/D converter in a digital CMOS process

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit feedback; sample and hold circuits; sampled data circuits; sigma-delta modulation; signal sampling; ΔΣ A/D converter; 2 micron; 5 MHz; current-mode ΔΣ ADC; current-mode circuits; delta-sigma ADC; digital CMOS process implementation; dynamic input signal; first-order structure; high-linearity sample/hold circuit; high-resolution ADC; oversampling current sample/hold structures; p-well CMOS process; sampled-data feedback architecture; second-order structure; CMOS process; Clocks; Current mode circuits; Feedback; Linearity; Nonlinear dynamical systems; Sampling methods; Signal processing; Signal sampling; Switches;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.661649

Filename

661649