• DocumentCode
    1343724
  • Title

    Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs

  • Author

    Zhang, En Xia ; Fleetwood, Daniel M. ; El-Mamouni, Farah ; Alles, Michael L. ; Schrimpf, Ronald D. ; Xiong, Weize ; Hobbs, Chris ; Akarvardar, Kerem ; Cristoloveanu, Sorin

  • Author_Institution
    Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN, USA
  • Volume
    57
  • Issue
    6
  • fYear
    2010
  • Firstpage
    3298
  • Lastpage
    3304
  • Abstract
    We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications.
  • Keywords
    CMOS integrated circuits; DRAM chips; radiation effects; silicon compounds; silicon-on-insulator; 1T-DRAM cells; CMOS devices; FinFET-based capacitor-less 1T-DRAMs; GIDL; SOI FinFETs; SiO2; SiO2 gate dielectric; TID; back-gate pulse; gate induced drain leakage; high-K gate dielectric; high-TID applications; memory sensing margin; metal gates; polycrystalline Si gates; programming methods; retention time; silicon-on-insulator; total ionizing dose radiation; DRAM chips; FinFETs; Logic gates; Sensitivity; Silicon on insulator technology; Transient analysis; 1T-DRAM; FinFETs; band-to-band tunneling; capacitor-less DRAM; floating body effects; gate induced drain leakage (GIDL); silicon-on-insulator (SOI);
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2075942
  • Filename
    5594977