• DocumentCode
    1343745
  • Title

    Comments on "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters"

  • Author

    Dempster, A.G. ; Macleod, M.D.

  • Author_Institution
    Dept. of Electron. Syst., Univ. of Westminster, London, UK
  • Volume
    45
  • Issue
    2
  • fYear
    1998
  • Firstpage
    242
  • Lastpage
    243
  • Abstract
    For the original paper see ibid., vol. 42 p. 453-460 (July 1995). In the aforementioned paper by D. Li, a method of designing integer multipliers that uses fewer adders than canonic signed-digit (CSD) coding was described. This method is claimed by the author to be optimal, i.e., it produces a multiplier with the least possible adders. The commenters claim that they have presented a similar method, implemented using the MAG algorithm, to perform the same task, which was shown to be optimal. Comparing the two techniques shows that Li´s method is not necessarily optimal. Both methods perform an exhaustive search over a set of multiplier configurations. In the commenters´ paper, they described these configurations in terms of graphs. It is said that this method proves to be quite useful in that it becomes easy to describe the cases not covered by Li´s algorithm. It is stated that the algorithm proposed by Li is suboptimal because: 1) graphs produced using fundamentals (intermediate vertices) of lower cost graphs are not considered; 2) tree-structured graphs are not considered; 3) right shifts (divide-by-two) are not allowed, causing some multipliers to require too many adders.
  • Keywords
    adders; digital arithmetic; digital filters; multiplying circuits; MAG algorithm; adders; integer multipliers; multiplier design; multiplierless digital filters; Adders; Algorithm design and analysis; Circuit topology; Costing; Costs; Design methodology; Digital filters; Signal processing algorithms; Tree data structures; Tree graphs;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.661661
  • Filename
    661661