A self-timed real-time sorting network

Author

Yun, Kenneth Y. ; James, Kevin W. ; Fairlie-Cuninghame, Robert H. ; Chakraborty, Supratik ; Cruz, Rene L.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA

Volume

8

Issue

3

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

356

Lastpage

363

Abstract

High-speed networks are expected to carry traffic classes with diverse quality of service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however, these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet switches that support a diverse mix of traffic. The sorting network receives packets with appropriately assigned priorities and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, and self-precharging domino logic to minimize the circuit latency. An experimental sorting network chip has been designed using the techniques described in this paper to support 10 Gb/s links with ATM-size packets.

Keywords

CMOS digital integrated circuits; VLSI; asynchronous circuits; asynchronous transfer mode; broadband networks; data communication equipment; digital communication; digital signal processing chips; packet switching; quality of service; real-time systems; scheduling; telecommunication computing; telecommunication traffic; 10 Gbit/s; ATM switches; diverse QoS guarantees; efficient resource utilization; high-speed networks; packet switches; quality of service guarantees; real-time sorting network; scheduling protocols; self-precharging domino logic; self-timed sorting network; traffic classes; Bandwidth; Delay; High-speed networks; Logic circuits; Packet switching; Protocols; Quality of service; Sorting; Switches; Telecommunication traffic;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.845903

Filename

845903