DocumentCode
1346065
Title
Wafer level chip scale packaging (WL-CSP): an overview
Author
Garrou, Philip
Author_Institution
Dow Chem. Co., Res. Triangle Park, NC, USA
Volume
23
Issue
2
fYear
2000
fDate
5/1/2000 12:00:00 AM
Firstpage
198
Lastpage
205
Abstract
Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP´s when underfill is not used than for equivalent flip chip parts. RambusTM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages
Keywords
DRAM chips; ball grid arrays; chip scale packaging; integrated circuit reliability; soldering; surface mount technology; Rambus DRAM; ball grid array; encapsulated technologies; flex tape; integrated passives; peripheral pad redistribution technology; reliability; solder ball attachment; wafer level chip scale packaging; wafer level test; Assembly; Chip scale packaging; Costs; Electronics packaging; Flip chip; Frequency; Hip; Packaging machines; Testing; Wafer scale integration;
fLanguage
English
Journal_Title
Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1521-3323
Type
jour
DOI
10.1109/6040.846634
Filename
846634
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