• DocumentCode
    1346126
  • Title

    A novel robust and low cost chips package and its thermal performance

  • Author

    Cho, Soon-Jin ; Park, Sang-Wook ; Park, Myung-Guen ; Kim, Deok-Hoon

  • Author_Institution
    Memory Res. Div., Hyundai Electron. Ind., Kyunggi, South Korea
  • Volume
    23
  • Issue
    2
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    257
  • Lastpage
    265
  • Abstract
    In an attempt to provide a high density memory solution, especially for workstation and PC servers, a stack chips package (SCP) has been developed. The major characteristics of SCP are as follows: (1) SCP contains a plurality of both memory chips and lead frames within a molded plastic package; (2) chip selection is made through the wire bonding option, resulting in the package with a memory capacity twice or four times that of monolithic chip; (3) plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface; and (4) SCP is found reliable and cost competitive when compared to other stack packages because it basically adopts the molded plastic packaging technology as well as the metal solder interconnection method. As electrical interconnection methods, both a fluxless soldering joint of Ag/Sn and a high-pressure mechanical joint of Ag were evaluated extensively and they successfully provided a reliable electrical conduction path without any signal degradation. Temperature cycle test and pressure cooker test were proved not to produce any micro cracks across the joint. The thermal performance of SCP was simulated by a thermal model based on finite element method (FEM) and also experimentally verified, showing good agreement within 10% deviation from simulated value. 128M SCP showed better thermal performance than stacked two TSOP´s because one chip could serve as a heat sink while the other chip is activated and thermal conduction path through the lead frame is short
  • Keywords
    finite element analysis; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated memory circuits; lead bonding; mechanical strength; plastic packaging; soldering; thermal analysis; Ag; Ag high-pressure mechanical joint; Ag/Sn fluxless soldering joint; AgSn; FEM-based thermal model; electroplated metal solders; finite element method; high density memory solution; lead frames; low cost package; metal solder interconnection method; molded plastic package; pressure cooker test; reliable electrical conduction path; robust package; stacked memory chips package; temperature cycle test; thermal performance; wire bonding option; Bonding; Costs; Lead; Plastic packaging; Robustness; Soldering; Testing; Thermal conductivity; Wire; Workstations;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/6040.846644
  • Filename
    846644