CMOS high speed interpolators based on parallel architecture

Author

Wang, Hong-wei ; Chan, Cheong-Fat ; Choy, Chiu-Sing

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China

Volume

46

Issue

2

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

326

Lastpage

329

Abstract

In our project, we design a series of interpolators, including twice, four-time and eight-time data interpolators. In our design, we adopt the parallel architecture to realize the circuits to make the speed of twice (×2), four-time (×4) and eight-time interpolators reach about 50, 40 and 30 MHz respectively. We use 0.8 μm double-metal single poly CMOS technology to fabricate our chips. To balance speed and accuracy of the interpolators, we use an eighth-order sine function as the interpolation function, and utilize the symmetry of sine function to simplify the structure of interpolator. The interpolating error is about 1.5%. The operating power voltage is 5 V and power dissipation is 70 mW at 50 MHz. The chips of our design are suitable for high speed digital signal processing, image processing and other applications

Keywords

CMOS digital integrated circuits; digital signal processing chips; image processing; interpolation; parallel architectures; 0.8 mum; 30 MHz; 40 MHz; 5 V; 50 MHz; 70 mW; CMOS high speed interpolators; accuracy; data interpolators; double-metal single poly CMOS technology; eighth-order sine function; high speed digital signal processing; image processing; interpolating error; interpolation function; parallel architecture; power dissipation; power voltage; sine function symmetry; speed; Circuits; Digital signal processing; Digital signal processing chips; Frequency; HDTV; Interpolation; Oscilloscopes; Parallel architectures; Sampling methods; Signal design;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.846665

Filename

846665