PC-based DTV architecture

Author

Iran, T. ; Moriarty, Mike ; Dao, Giang ; Welker, Mark

Author_Institution

Dept. of Adv. Eng., Compaq Comput. Corp., Houston, TX, USA

Volume

46

Issue

2

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

330

Lastpage

333

Abstract

This paper presents the first PC-based DTV architecture using an industry standard PCI bus to transfer decoded video data from a DTV decoder to the graphics subsystem of a multimedia PC. The proposed architecture eliminates: (1) the need for a dedicated video port cable between a PC-based DTV decoder and a graphics controller, and (2) the need for a nonstandard graphics controller video port. This paper also presents a novel concept of bursting the decoded DTV data over the PCI bus with no visible video artifacts due to bus latency or different video/graphics refresh rates. In normal operation, this architecture consumes only about 31% of the bandwidth of a 33 MHz 32-bit PCI bus

Keywords

digital television; microcomputer applications; multimedia communication; multimedia computing; system buses; telecommunication computing; telecommunication terminals; video coding; 32 bit; 33 MHz; DTV decoder; PC-based DTV architecture; bandwidth; decoded DTV data; decoded video data; graphics controller; graphics subsystem; industry standard PCI bus; multimedia PC; video/graphics refresh rates; Bandwidth; Clocks; Computer architecture; Computer graphics; Decoding; Delay; Digital TV; Displays; Logic; Synchronization;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.846666

Filename

846666