A Digitally Corrected 5-mW 2-MS/s SC $\Delta \Sigma$ ADC in 0.25- $\mu$ m CMOS With 94-dB SFDR

A digital correction scheme that allows a switched-capacitor (SC) ΔΣ ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, nonlinear settling errors cause increasing harmonic distortion. The correction technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With correction, experimental results yield a peak SNDR of 75 dB, a THD of -90 dB and a SFDR of 94 dB. The total analog power dissipation of the corrected modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncorrected modulator output. The active area is 0.39 mm² in 0.25-μ m CMOS.