DocumentCode
1346955
Title
2.6 kV 4H-SiC lateral DMOSFETs
Author
Spitz, J. ; Melloch, M.R. ; Cooper, J.A., Jr. ; Capano, M.A.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
19
Issue
4
fYear
1998
fDate
4/1/1998 12:00:00 AM
Firstpage
100
Lastpage
102
Abstract
A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.
Keywords
ion implantation; power MOSFET; silicon compounds; wide band gap semiconductors; 2.6 kV; 4H-SiC lateral DMOSFET; SiC; blocking voltage; field effect transistor; insulating 4H-SiC substrate; lateral double-implanted MOSFET; lightly doped n-epilayer; Annealing; Argon; Boron; FETs; Implants; Insulation; MOSFET circuits; Nitrogen; Silicon carbide; Voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.663527
Filename
663527
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