Fully self-aligned tri-layer a-Si:H thin-film transistors with deposited doped contact layer

Author

Thomasson, D.B. ; Jackson, T.N.

Author_Institution

Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA

Volume

19

Issue

4

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

124

Lastpage

126

Abstract

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n/sup +/ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V/sub DS/=0.1 V) and saturation region (V/sub DS/=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10/sup 7/.

Keywords

amorphous semiconductors; carrier mobility; elemental semiconductors; hydrogen; photolithography; semiconductor device metallisation; silicon; thin film transistors; 0.1 V; 13 nm; 20 micron; 25 V; Si:H; backside exposure photolithography steps; contact overlaps; deposited doped contact layer; extrinsic mobility values; fully self-aligned tri-layer TFTs; linear region; off currents; on/off current ratio; saturation region; short channel TFT; Active matrix liquid crystal displays; Amorphous silicon; Doping; Etching; Fabrication; Lithography; Manufacturing processes; Parasitic capacitance; Semiconductor films; Thin film transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.663535

Filename

663535