DocumentCode
1347251
Title
A 102-dB spurious-free DR ΣΔ ADC using a dynamic dither scheme
Author
Gomez, Gabriel J.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
Volume
47
Issue
6
fYear
2000
fDate
6/1/2000 12:00:00 AM
Firstpage
531
Lastpage
535
Abstract
A sigma-delta analog-to-digital converter (ADC) using dynamic dither to achieve a tone-free dynamic range of 102 dB in an audio bandwidth is presented. The design was implemented using a third-order 2:1 cascade architecture with an oversampling ratio of 128. The ADC modulator consumes 22 mW from a 3.0 V power supply, and was fabricated in 0.6-μm CMOS (analog portion) and 0.3-μm CMOS (digital portion) using multichip-module technology
Keywords
CMOS integrated circuits; audio signal processing; cascade networks; multichip modules; sigma-delta modulation; 0.3 micron; 0.6 micron; 22 mW; 3.0 V; CMOS; audio bandwidth; dynamic dither scheme; multichip-module technology; oversampling ratio; spurious-free DR sigma-delta ADC; third-order 2:1 cascade architecture; tone-free dynamic range; Analog-digital conversion; CMOS process; CMOS technology; Capacitors; Circuits; Codecs; Digital modulation; Dynamic range; Instruments; Power supplies;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.847068
Filename
847068
Link To Document