High-throughput block-matching VLSI architecture with low memory bandwidth

A full-search block-matching architecture which features high throughput, low data input lines, and low memory bandwidth is proposed. It reduces memory I/O requirements by the maximum reuse of search data using on-chip memory. It also promises a high throughput rate by the continuous calculation of all block distortions in a search area using two search data input flows without processing any invalid block distortion, and by the continuous process of the neighbored reference blocks removing the initialization period between blocks. The processor for -16/+15 search ranges, implemented in the total 220 k gates using 0.6 μm triple-metal CMOS technology, can operate at a 66 MHz clock rate, and therefore is capable of encoding H.263(4CIF), MPEG2(MP@ML), and other multimedia applications