Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]

Author

Murthy, C.S. ; Gall, M.

Author_Institution

IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA

Volume

16

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1383

Lastpage

1389

Abstract

This paper describes the first study of the complete sequence from process simulation to circuit performance and the corresponding sensitivities for 0.25-μm technology. This is made possible by a combination of physically based process models and a systematic calibration involving SIMS, one-dimensional (1-D), and two-dimensional (2-D) device characteristics. Simulated nFET and pFET characteristics match hardware (HW) within 5-10% for both long-channel and nominal length devices. Simulated ring-oscillator performance is in good agreement with HW data. Sensitivities of device characteristics and the inverter gate delay to process variations (within 10%) are quantified. These investigations establish the correlation between process variations and circuit performance

Keywords

DRAM chips; calibration; circuit CAD; digital simulation; semiconductor process modelling; 0.25 micron; 1D device characteristics; 256 Mbit; 2D device characteristics; DRAMs; TCAD simulation; circuit performance; inverter gate delay; long-channel devices; nominal length devices; physically based process models; process simulation; process variation effects; ring-oscillator performance; systematic calibration; Algorithm design and analysis; Books; Circuit optimization; Circuit simulation; Field programmable gate arrays; Logic testing; Programmable logic arrays; Programmable logic devices; Routing; Switches;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.663828

Filename

663828