A 2 $,\times,$ 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet

A 2 × 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate <;10^-12 with 20-mV_pp input sensitivity, consuming a total power of 510 mW from a 1.2-V supply.