• DocumentCode
    1348727
  • Title

    A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)

  • Author

    Gjanci, Juliana ; Chowdhury, Masud H.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Illinois at Chicago, Chicago, IL, USA
  • Volume
    19
  • Issue
    11
  • fYear
    2011
  • Firstpage
    1949
  • Lastpage
    1959
  • Abstract
    Conventional off-chip or single-stage on-chip converter will fail to meet the demand for different supply voltage domains for various functional blocks/cores in traditional or future multi-/many-core system-on-a-chips (SOCS). In this paper, a hybrid two-stage voltage regulation scheme is proposed, where the first stage consists of a switching voltage regulator located off-chip, and the second stage consists of a tree structure of linear regulators located on the chip. This approach proves to be efficient, simple and less costly compared to other options that offer total on-chip integration of a switching regulators. The difficulties and limitations of on-chip switching regulator have been analyzed. For the tree structure of on-chip linear regulators two different architectures (cascaded and parallel) have been proposed. It is demonstrated that a cascaded tree of linear regulators is a better solution than a parallel tree structure from performance point of view.
  • Keywords
    convertors; system-on-chip; voltage control; conventional off-chip converter; functional block-core; hybrid two-stage voltage regulation scheme; multimany-core SOC; multimany-core system-on-a-chip; on-chip linear regulator; on-chip switching voltage regulator; parallel tree structure; single-stage on-chip converter; supply voltage domain; total on-chip integration; Capacitors; Inductors; Regulators; Resistance; Switches; System-on-a-chip; Voltage control; Hybrid regulator; low dropout regulator; multicore; on-chip voltage regulator; switching regulator; system-on-a-chip (SOC);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2010.2072997
  • Filename
    5599893