Gate Charge Control for MOSFET Turn-Off in PWM Motor Drives Through Empirical Means

The following paper presents a novel, empirical approach to gate charge control of a MOSFET used in low-side drive applications such as found in dc motor drives during turn-off, using pulsewidth modulation (PWM) based on ideal expressions of MOSFET behavior during turn- off. Without gate charge control, ringing and overshoot caused by dv /dt effects during the turn-off can result in an increase in electromagnetic interference as well as an increased power dissipation. The ringing can be difficult to suppress through the addition of suppression components as they add cost and bulk to the motor controller. Previous work has focused on the observation of dv/ dt, feed-forward, or open-loop means. Although complex gate charge solutions exist in dedicated application-specific integrated circuits (ASICs), a simple, cost-effective solution is proposed in this paper. This solution differs from previous solutions, making use of the ideal relationship between the drain-to-source and gate-to-source voltage of the MOSFET on turn-off to determine the region of high dv/dt to control a two-staged gate charge removal scheme. This solution can be readily implemented in microprocessor-based control schemes used to control motor drives and switch-mode power supplies utilizing low-side MOSFET switching. Circuit operation and advantages are presented and supported by simulation and experimental results.