Efficient hierarchical chaotic image encryption algorithm and its VLSI realisation

Author

Yeo, J.-C. ; Guo, J.-I.

Author_Institution

Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miaoli, Taiwan

Volume

147

Issue

2

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

167

Lastpage

175

Abstract

An efficient hierarchical chaotic image encryption algorithm and its VLSI architecture are proposed. Based on a chaotic system and a permutation scheme, all the partitions of the original image are rearranged and the pixels in each partition are scrambled. Its properties of high security, parallel and pipeline processing, and no distortion are analysed. To implement the algorithm, its VLSI architecture with pipeline processing, real-time processing capability, and low hardware cost is designed and the FPGA realisation of its key modules is given. Finally, the encrypted image is simulated and its fractal dimension is computed to demonstrate the effectiveness of the proposed scheme

Keywords

VLSI; chaos; cryptography; field programmable gate arrays; fractals; image coding; parallel algorithms; parallel architectures; pipeline processing; FPGA realisation; VLSI architecture; VLSI realisation; efficient algorithm; fractal dimension; hierarchical chaotic image encryption algorithm; high security; image partitions; low hardware cost; parallel processing; permutation scheme; pipeline processing; pixels scrambling; real-time processing capability;

fLanguage

English

Journal_Title

Vision, Image and Signal Processing, IEE Proceedings -

Publisher

iet

ISSN

1350-245X

Type

jour

DOI

10.1049/ip-vis:20000208

Filename

848579