Evaluating the Signal-Reliability of Logic Circuits

A different approach to the evaluation of signal reliability of digital logic circuits is presented. The method derives functional descriptions of each output of the circuit. In order to include the effect of faults in the function realized by the circuit, three binary variables are used to specify the state of each line in the circuit. This approach provides a different insight into the problem of digital system reliability. The difficulty of this method is the complexity of probability expression for a large circuit. The calculations will be lessened when we introduce the concept of bundling. But no existing method can reduce the calculations drastically.