• DocumentCode
    1353823
  • Title

    Parallel CRC generation

  • Author

    Albertengo, Guido ; Sisto, Riccardo

  • Author_Institution
    Electron. Dept., Politecnico di Torino, Italy
  • Volume
    10
  • Issue
    5
  • fYear
    1990
  • Firstpage
    63
  • Lastpage
    71
  • Abstract
    Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. A few interesting application areas for hardware parallel encoders are pointed out.<>
  • Keywords
    digital arithmetic; encoding; digital system theory; encoding cyclic redundant codes; generator polynomial; hardware parallel encoders; logic equations; z-transforms; Backplanes; Communication system control; Cyclic redundancy check; Data communication; Digital systems; Equations; Hardware; Logic circuits; Polynomials; Shift registers;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.60527
  • Filename
    60527
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1353823