DocumentCode
1354524
Title
Modelling delay and crosstalk in VLSI interconnect for electrical simulation
Author
Maffezzoni, P. ; Branbilla, A.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Volume
36
Issue
10
fYear
2000
fDate
5/11/2000 12:00:00 AM
Firstpage
862
Lastpage
864
Abstract
A method for extracting the multi-pen equivalent network of a system of m distributed RC lines is presented. The technique enables the time delays and crosstalk between interconnects to be efficiently analysed by employing conventional circuit simulators
Keywords
delays; VLSI interconnect; circuit simulators; crosstalk; delay; distributed RC lines; electrical simulation; multi-pen equivalent network;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20000676
Filename
850493
Link To Document