• DocumentCode
    1354546
  • Title

    Endurance of EEPROMs with On-Chip Error Correction

  • Author

    Haifley, Tim

  • Author_Institution
    EXAR Corporation; 2150 Commerce Drive; San Jose, California 95131 USA.
  • Issue
    2
  • fYear
    1987
  • fDate
    6/1/1987 12:00:00 AM
  • Firstpage
    222
  • Lastpage
    223
  • Abstract
    This paper presents an endurance model for EEPROMs utilizing an on-chip error-correction code (ECC). This is necessary to determine the effect that ECC schemes have upon endurance (and therefore, reliability) of EEPROMs. EEPROM technology is briefly discussed.
  • Keywords
    Dielectric devices; EPROM; Error correction; Error correction codes; Integrated circuit modeling; Manufacturing; Nonvolatile memory; Semiconductor memory; Voltage; Weibull distribution; Electrically-erasable programmable read-only memory (EEPROM); Endurance; Error correction code (ECC); Floating gate; Neutral state; Q-cell; Tunnel dielectric (TD);
  • fLanguage
    English
  • Journal_Title
    Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9529
  • Type

    jour

  • DOI
    10.1109/TR.1987.5222346
  • Filename
    5222346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1354546