Passive Equalizer Design for Through Silicon Vias With Perfect Compensation

This paper proposes a novel passive equalizer which is composed of a parallel resistance-capacitance (RC) circuit and capable of perfect compensation for lossy effects of through silicon via (TSV). To design the equalizer, the conventional transmission line theory is utilized to derive an analytic circuit model of the TSV which is verified by numerical methods. Based on the analytic circuit model, the significance analysis is performed to acquire a much simplified capacitance-conductance circuit model which is employed to construct the design formula for the RC equalizer with perfect compensation. A ten-stacked TSV in series with the designed equalizer is taken as an example to demonstrate the resultant improvement in the eye diagram, namely, nearly zero timing jitter and three times enlarged eye opening.