A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a 1-micrometer silicon-film-on-insulator-on-silicon

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented