An interpolating clock synthesizer

Author

Bazes, Mel ; Ashuri, Roni ; Knoll, Ernest

Author_Institution

Intel Israel Ltd., Haifa, Israel

Volume

31

Issue

9

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

1295

Lastpage

1301

Abstract

A digital alternative to analog phase-locked loop (PLL)-based clock generators for microprocessors, denoted an interpolating clock synthesizer (ICS), is described. Using ROM-based digital waveform synthesis, the ICS implements a wide range of frequency multiples having the form P/Q, where P and Q are integers. The ICS outputs two synthesized clocks, one for the I/O interface having a 1/1 frequency multiple and one for the core having one of eight dynamically-selectable frequency multiples (1/1, 3/2, 5/3, 2/1, 5/2, 3/1, 15/4, and 5/1). The ICS uses a synchronous delay line as a coarse (T_p/30) timing reference, while through digital delay interpolation it achieves a fine delay resolution of 0.04 ns. Using a completely digital precision phase detector, the ICS achieves a DC skew of ±0.05 ns

Keywords

CMOS digital integrated circuits; delay circuits; interpolation; microprocessor chips; timing circuits; waveform generators; 0.04 ns; ROM-based digital waveform synthesis; digital delay interpolation; digital precision phase detector; fine delay resolution; interpolating clock synthesizer; microprocessors; synchronous delay line; timing reference; Clocks; Delay lines; Frequency conversion; Frequency synthesizers; Interpolation; Microprocessors; Phase detection; Phase locked loops; Read only memory; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.535413

Filename

535413