Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits by 68%, however, requires a unique write operation that updates the check-bits by writing one data word while reading the other three data words. The ground potential of the composite word is raised to a nonzero value during retention in order to limit the leakage power consumption. A critical charge-based soft error rate (SER) model is proposed to estimate the resulting increase in the SER. Both the MECC scheme and the SER model are verified by implementing a 64-kb SRAM macro in 90 nm CMOS technology. The SRAM consumes 5.34 pJ energy with a data latency of 3.3 ns, thus showing up to 82% per-bit energy saving and 8x speed improvement over previously reported multiword ECC schemes. Accelerated neutron radiation test of the SRAM confirms 85% soft error correction by the MECC and 90% accuracy of the SER model.