RNS-FPL merged architectures for orthogonal DWT

Author

Ramírez, J. ; García, A. ; Fernández, P.G. ; Patrilla, L. ; Lloris, A.

Author_Institution

Dept. de Ingenieria Electr., Campus Univ. Fuenternueva, Granada, Spain

Volume

36

Issue

14

fYear

2000

fDate

7/6/2000 12:00:00 AM

Firstpage

1198

Lastpage

1199

Abstract

Novel, regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1D discrete wavelet transform (DWT) and 1D inverse discrete wavelet transform (1DWT) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. They are suitable to be considered as the core of 2D DWT processors for high data rate image processing applications

Keywords

discrete wavelet transforms; field programmable gate arrays; image processing; optical logic; table lookup; 1D inverse discrete wavelet transform; 2D DWT processors; RNS-FPL merged architectures; easily scalable residue number system; field-programmable logic merged architectures; filter coefficient precision; high data rate image processing applications; input data; look-up tables; orthogonal 1D discrete wavelet transform; orthogonal DWT; sustained throughput;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20000896

Filename

852238