• DocumentCode
    1361030
  • Title

    Reliability test procedures: LSI circuits: Fault models make high-volume testing practical

  • Author

    Bernhard, Robert

  • Volume
    18
  • Issue
    10
  • fYear
    1981
  • Firstpage
    67
  • Lastpage
    72
  • Abstract
    The testing of large-scale-integrated circuits is a major factor in the cost of producing such digital devices as memory chips and microprocessors. Manufacturers could test earlier small- and medium-scale-integrated devices cheaply and exhaustively ¿ testing every possible state that the circuits could take up ¿ but they cannot do the same with LSI and very large-scale-integrated devices, because of the awesome number of states. For example, a 4096-bit random-access memory can have a total number of states, or combinations, of 2 raised to the 4096th power. With current test equipment operating at 10 megahertz, it would take an astronomical amount of time to test for every memory combination.
  • Keywords
    Circuit faults; Integrated circuit modeling; Military aircraft; Random access memory; Reliability; Space vehicles; Testing;
  • fLanguage
    English
  • Journal_Title
    Spectrum, IEEE
  • Publisher
    ieee
  • ISSN
    0018-9235
  • Type

    jour

  • DOI
    10.1109/MSPEC.1981.6369640
  • Filename
    6369640