DocumentCode
1363097
Title
Area-time optimal adder design
Author
Wei, Belle W Y ; Thompson, Clark D.
Author_Institution
Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
Volume
39
Issue
5
fYear
1990
fDate
5/1/1990 12:00:00 AM
Firstpage
666
Lastpage
675
Abstract
A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS
Keywords
CMOS integrated circuits; VLSI; adders; digital arithmetic; dynamic programming; logic design; 66 bit; VLSI parallel adder; area-time optimal adder design; component cells; dynamic programming; floating-point processor; modular design; static CMOS; Adders; CMOS logic circuits; CMOS technology; Delay; Design optimization; Dynamic programming; Heart; Integrated circuit interconnections; Logic design; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.53579
Filename
53579
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