Application of Generalized Linear Models to Predict Semiconductor Yield Using Defect Metrology Data

Semiconductor yield modeling is essential to identify processing issues, improve quality, and meet customer demand. However, the massive amounts of data collected during the fabrication process and the number of historical models available make yield modeling a complex and challenging task. This paper presents a methodology to guide the practitioner in determining what data should be collected, integrated, and aggregated, followed by a modeling strategy to forecast yield using generalized linear models based on defect metrology data. This technique yields results at both the die and the wafer levels, significantly outperforms existing models found in the literature based on prediction errors, and identifies significant factors that can drive process improvement. This method also allows the nested structure of the process to be considered in the model, improving predictive capabilities and violating fewer assumptions. An example is presented to discuss this approach and to demonstrate the advantages of these models over the models of the past.