The Layout Geometry Dependence of the Power Cells on Performances and Reliability

The performances and reliability of the NMOS power cells for power amplifiers (PA) were proposed. The performances of power cells with different layout geometries have been compared. The drain current degradation of the NMOS transistors due to hot-carrier effect and high RF power stresses induced by the load impedance mismatches was also present in this work. The load mismatch factors at fundamental, second-order, and third-order frequencies were analyzed to quantify the power mismatch. The cells were fabricated by a 0.18 μm CMOS process. All of the characteristics of the devices were measured at 5.2 GHz.