Modeling IC Snapback Characteristics Under Electrostatic Discharge Stress

This paper presents a novel technique for modeling the electrostatic discharge snapback phenomenon in integrated circuits (ICs). The macromodel is built using standard components: BSIM3v3.2 model for the MOSFET, a bipolar transistor modeled by Mextram 504.7, and a substrate resistor. The IC under test is characterized by its die and package impedance. The model should allow easier simulation program with IC emphasis implementation, high simulation speed, less convergence issues, and wider availability of a gate-grounded n-type MOSFET protection device. Our model determines the interaction between the protection device and the internal circuitry of the IC. The model parameters are extracted with MATLAB script. Simulation results are compared with transmission-line pulsing measurement for a voltage regulator NCV4949 and a controller area network transceiver TLE6250G.