Package thermal resistance: geometrical effects in conventional and hybrid packages

The effect of package geometry on thermal resistance for a set of six package configurations is studied. With thermal resistance network models it is possible to determine the junction-to-ambient thermal resistance for each package type under a variety of external cooling conditions. It is found that as the external package cooling technology improves, the thermal resistances for different package configurations separate into distinct ranges. In general, packages which have the lowest thermal resistance under free convection will have the largest thermal resistance under conditions of advanced forced liquid cooling, and vice versa. It is found that the surface area and internal thermal resistance serve as good indicators of thermal performance throughout the range from natural convection to microchannel cooling. On the basis of simple models, nonuniform chip active layer temperature distribution, spatially localized hot spot formation, and the effect of lower chip-to-ambient thermal resistance on the chip temperature profile are discussed