High-density chain ferroelectric random access memory (chain FRAM)

Author

Takashima, Daisaburo ; Kunishima, Iwao

Author_Institution

Adv. Semicond. Devices Labs., Toshiba Corp., Yokohama, Japan

Volume

33

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

787

Lastpage

792

Abstract

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F² size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V_dd cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation

Keywords

cellular arrays; ferroelectric capacitors; ferroelectric storage; random-access storage; 45 ns; 70 ns; access time; block selecting transistor; chain FRAM; chain ferroelectric random access memory; chip size; cycle time; driven cell-plate scheme; ferroelectric capacitor; nondriven half-V_dd cell-plate scheme; plural memory cells; Capacitors; Fabrication; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Polarization; Random access memory; Read-write memory; Tin; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.668994

Filename

668994