An efficient CMOS bridging fault simulator: with SPICE accuracy

Author

Di, Chennian ; Jess, Jochen A G

Author_Institution

Fac. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands

Volume

15

Issue

9

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

1071

Lastpage

1080

Abstract

This paper presents an alternative modeling and simulation method for CMOS bridging faults. The significance of the method is the introduction of a set of generic-bridge tables which characterize the bridged outputs for each bridge and a set of generic-cell tables which characterize how each cell propagates a logically undefined input. These two sets of tables are derived dynamically for a specific design by using a SPICE circuit simulator. Then they can be used by any logic fault simulator to simulate bridging faults. In this way, the proposed method can perform very fast bridging fault simulation yet with SPICE accuracy. The paper shows how these two sets of tables are derived and used in a parallel pattern fault simulator. Experimental results on ISCAS85 benchmarks are promising

Keywords

CMOS logic circuits; SPICE; circuit analysis computing; fault diagnosis; integrated circuit modelling; logic testing; CMOS bridging fault; ISCAS85 benchmarks; SPICE accuracy; SPICE circuit simulator; generic-bridge tables; generic-cell tables; logic fault simulator; logically undefined input; parallel pattern fault simulator; Bridge circuits; CMOS integrated circuits; Circuit faults; Circuit simulation; Computational modeling; Integrated circuit manufacture; Logic; SPICE; Semiconductor device modeling; Switches;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.536713

Filename

536713