TLM: a trench leakage monitor for a four megabit SPT DRAM technology

Author

Voldman, Steven H. ; Long, Christopher W.

Author_Institution

IBM, Essex Junction, VT, USA

Volume

4

Issue

3

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

226

Lastpage

232

Abstract

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology

Keywords

CMOS integrated circuits; DRAM chips; integrated circuit manufacture; integrated circuit testing; leakage currents; production testing; 4 Mbit; CMOS; SPT DRAM technology; Si defects; cell retention yield; dynamic RAM; macro-array structure; manufacturing test vehicle; nonaddressable array; random access memory; semiconductor process; single trench capacitor; storage node parasitic device characterization; substrate plate trench capacitor; trench leakage monitor; CMOS process; CMOS technology; Capacitors; DRAM chips; Monitoring; Random access memory; Semiconductor device manufacture; Silicon; Testing; Vehicles;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.85944

Filename

85944