• DocumentCode
    1371193
  • Title

    Path sensitisation and gate sizing approach to low power optimisation

  • Author

    Kim, Juho ; Yang, Jaesok ; Hwang, Sun-Young

  • Author_Institution
    Dept. of Comput. Sci., Sogang Univ., Seoul, South Korea
  • Volume
    34
  • Issue
    7
  • fYear
    1998
  • fDate
    4/2/1998 12:00:00 AM
  • Firstpage
    619
  • Lastpage
    620
  • Abstract
    A powerful circuit optimisation solution for high-performance and low-power design is presented. The proposed method combines path sensitisation and gate resizing approaches to reduce the power dissipation under a given timing constraint. The algorithm is tested on ISCAS-85 benchmark circuits, and up to 30%, power reduction is achieved
  • Keywords
    circuit layout CAD; circuit optimisation; digital integrated circuits; integrated circuit layout; logic CAD; circuit optimisation solution; gate sizing; low power optimisation; low-power design; path sensitisation; timing constraint;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980473
  • Filename
    673753
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1371193