DocumentCode
1373228
Title
Fault-tolerant Newton-Raphson and Goldschmidt dividers using time shared TMR
Author
Gallagher, W. Lynn ; Swartzlander, Earl E., Jr.
Author_Institution
Cirrus Logic, Austin, TX, USA
Volume
49
Issue
6
fYear
2000
fDate
6/1/2000 12:00:00 AM
Firstpage
588
Lastpage
595
Abstract
Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt´s algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided into thirds, and the rest of the divider logic replicated around each part, to provide three independent dividers. While this reduces the size of the fault-tolerant dividers over that of traditional TMR, latency may be increased. However, both division algorithms can be modified to use lower precision multiplications during the early iterations. This saves multiply cycles and, hence, produces a faster divider
Keywords
digital arithmetic; dividing circuits; error correction; fault tolerant computing; Goldschmidt dividers; concurrent error correction; fault-tolerant Newton-Raphson dividers; hardware multiplier; iterative division algorithms; time shared triple modular redundancy; Arithmetic; Circuit faults; Delay; Error correction; Fault tolerance; Fault tolerant systems; Hardware; Iterative algorithms; Read only memory; Redundancy;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.862218
Filename
862218
Link To Document