DocumentCode
1373425
Title
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
Author
Medeiro, Fernando ; Perez-Verdu, Belen ; de la Rosa, Jos M. ; Rodriguez-Vazquez, Angel
Author_Institution
Inst. de Microelectron., CSIC, Seville
Volume
34
Issue
5
fYear
1998
fDate
3/5/1998 12:00:00 AM
Firstpage
422
Lastpage
424
Abstract
The authors present a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantisation in a cascade architecture to obtain high resolution with a low oversampling ratio. It is less sensitive to the nonlinearity of the digital-to-analogue (DAC) than those previously reported, thus enabling the use of very simple analogue circuitry with neither calibration nor trimming required
Keywords
cascade networks; sigma-delta modulation; DAC error sensitivity; analogue circuitry; high-speed A/D conversion; multi-bit cascade ΣΔ modulator; oversampling ratio; resolution;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980270
Filename
674189
Link To Document