• DocumentCode
    1373515
  • Title

    High-speed parallel-prefix module 2n-1 adders

  • Author

    Kalampoukas, Lampros ; Nikolos, Dimitris ; Efstathiou, Costas ; Vergos, Haridimos T. ; Kalamatianos, John

  • Author_Institution
    Xebeo Commun. Inc., South Plainfield, NJ, USA
  • Volume
    49
  • Issue
    7
  • fYear
    2000
  • fDate
    7/1/2000 12:00:00 AM
  • Firstpage
    673
  • Lastpage
    680
  • Abstract
    A novel parallel-prefix architecture for high speed module 2n -1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures
  • Keywords
    adders; digital arithmetic; CMOS implementations; carry look-ahead structures; high-speed parallel-prefix module 2n-1 adders; parallel-prefix architecture; Adders; Application software; Circuits; Computer architecture; Concurrent computing; Delay; Fault tolerant systems; Logic; Signal generators; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.863036
  • Filename
    863036
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1373515