Moving Boundary Simulation and Experimental Verification of High Aspect-Ratio Through-Silicon-Vias for 3-D Integration

Because of the pinch-off effect, filling high aspect- ratio, void- and seam-free through-silicon-vias (TSVs) using damascene copper electroplating is one of the technical challenges in realizing 3-D integration and packaging. This paper presents simulation investigation and experimental verification of bottom-up copper electroplating (BCE) to verify its capability in fabricating high aspect-ratio void-free TSVs. Theoretical models for blind- and through-via copper electroplating are derived, and a generic solving method is developed by employing a moving boundary simulation to address the challenge of time-dependent process. The time-resolved evolution of electroplating profiles is simulated after the ion concentration distribution and the electric current density are obtained. The simulation results predict the behaviors of copper electroplating of blind- and through-vias, and reveal the mechanism of void formation. By employing a transfer wafer to provide seed layers, improved BCE is developed and high aspect-ratio void-free TSVs are successfully fabricated. The experimental results verify the theoretical model and the moving boundary simulation method, and prove the capability of BCE in filling high aspect-ratio TSVs.