A novel frame reordering scheme and a high speed VLSI architecture of multiple reference frame motion estimator for H.264/AVC

In this paper, we propose a novel frame reordering scheme and a high speed VLSI architecture of full search variable block size motion estimator (VBSME) supporting multiple reference frames. In the proposed architecture, four current macrobocks are concurrently compared with a single search window (SW) of the reference frame to find the best matched block. By scheduling the order of the reference frame in pipeline, the proposed architecture can reduce the memory bandwidth and the execution time. Also, the proposed architecture can fully reuse the overlapped searching area in the horizontal direction to reduce the memory bandwidth and obtain 100% hardware utilization of the frame level by using the meander-like scan and the method of MB-level data reuse. Then, 71.73% of local memory size and 69.34% of system memory bandwidth were saved compared with non pipelined-multiple reference frame motion estimation (NP-MRFME). Under an operating frequency of 112.32 MHz, the architecture can support the real-time processing of 1280 × 720 picture size at 30 fps with the search area of [-16, +15].