Pass-transistor adiabatic logic with NMOS pull-down configuration

A new low power adiabatic logic family, pass-transistor adiabatic logic with NMOS pull-down configuration, is presented. For a 2:1 multiplexer, a power saving of ~800% is achieved, compared to a 2N-2N2P logic circuit at 20 MHz. Compared to pass-transistor adiabatic logic using single power-clock supply (PAL), the `tri-state´ problem is solved, while power consumption is comparable. A four phase sinusoidal clock power supply is employed in the new logic family, which facilitates pipelining hence leading to higher throughput, compared to PAL