Design of a Low Voltage-Low Power 3.1–10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology

Author

Simitsakis, Paschalis ; Papananos, Yannis ; Kytonaki, Eleni-Sotiria

Author_Institution

Sch. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece

Volume

57

Issue

11

fYear

2010

Firstpage

833

Lastpage

837

Abstract

In this brief, the design of a 3.1 to 10.6 GHz ultra wideband (UWB) RF front-end (RFFE) is presented. It employs a novel low noise common gate amplifier combined with a noise canceling circuit, that provides wideband input matching, high voltage gain and low noise figure in the whole band of operation. It also adopts a passive single balanced direct conversion mixer with a custom designed balun at its local oscillator (LO) input. The RFFE achieves 20.6 dB of voltage gain and it has adequately flat frequency response. Its noise figure is 3-3.8 dB and the CP1 at the input is -19.7 dBm. The circuit consumes only 10.8 mW from a 1.2 V supply and it was designed in IBM´s CMOS 65 nm process.

Keywords

CMOS integrated circuits; MMIC amplifiers; MMIC mixers; field effect MMIC; low noise amplifiers; low-power electronics; ultra wideband technology; CMOS technology; UWB RF front-end; frequency 3.1 GHz to 10.6 GHz; low noise common gate amplifier; noise canceling circuit; noise figure 3 dB to 3.8 dB; passive single balanced direct conversion mixer; power 10.8 mW; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Gain; Logic gates; Mixers; Noise; Radio frequency; Transistors; Common gate; RF front-end (RFFE); direct conversion mixer; noise cancelling; ultra wideband (UWB);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2082910

Filename

5638130