DocumentCode
1379684
Title
Reduced complexity analogue-to-residue conversion employing folding number system
Author
Pham, D.-M. ; Premkumar, A.B. ; Madhukumar, A.S.
Author_Institution
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
Volume
4
Issue
1
fYear
2010
fDate
1/1/2010 12:00:00 AM
Firstpage
30
Lastpage
41
Abstract
Digital signal processing (DSP) algorithms are computationally intensive and require recursive multiplication and addition. Residue number systems (RNS) offer significant advantages over conventional number systems when used in the design of special purpose DSP architectures. However, conversion of analogue signals into their residue equivalents requires first converting the signal to binary equivalents and subsequently using modular circuits to convert the resultant binary to residues. A new number system called the folding number system (FNS) is proposed and used as the basis for residue conversion. Since FNS has one-to-one correspondence with RNS, the proposed method converts the analogue signal to its RNS equivalents using concealed symmetrical residues in FNS domain. The conversion is simple and uses analogue folding circuits, comparators and combinatorial logic circuits. High-frequency analogue signals can be efficiently converted thus enabling RNS to be implemented in high-speed signal processing architectures.
Keywords
combinational circuits; comparators (circuits); computational complexity; digital signal processing chips; residue number systems; DSP architectures; analogue folding circuits; analogue signal conversion; combinatorial logic circuits; comparators; concealed symmetrical residue; digital signal processing algorithm; folding number system; high-frequency analogue signals; high-speed signal processing architectures; modular circuits; residue number systems;
fLanguage
English
Journal_Title
Circuits, Devices & Systems, IET
Publisher
iet
ISSN
1751-858X
Type
jour
DOI
10.1049/iet-cds.2009.0129
Filename
5378436
Link To Document