The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603 and PowerPC 604 RISC microprocessors

Thermal resistance networks or “compact” models of the PowerPC 603 and PowerPC 604 microprocessors in controlled-collapsed-chip-connection/ceramic-ball-grid-array (C4/CBGA) single-chip package are derived from “detailed” three-dimensional (3-D) conduction models of the parts by both analytical and data fitting techniques. The behavioral correctness of these models is assessed by comparing the die-junction temperatures predicted for the compact model with the detailed model results for a range of boundary conditions applied at the surfaces of the package. The performance of these models is then verified by comparing the detailed and compact models in an application-specific environment (a wind tunnel) using a computational-fluid dynamics program. The interaction between the package and its environment is also discussed. The work reported here forms part of a long term European research program to create and validate generic thermal models of a range of electronic parts